1. Field of the Invention
The present invention relates to a photomask, such as a photomask for forming gate lines on a semiconductor substrate, and a method of manufacturing a semiconductor device using the photomask.
2. Description of the Related Art
Photomasks include pattern information used for transferring shapes of various patterns onto a silicon wafer for fabricating semiconductor devices. Therefore, the most fundamental task of forming fine patterns of semiconductor devices is dependent upon photomasks. Typically all patterns of semiconductor devices are formed by photolithography processes that use photomasks.
FIG. 1A is a conventional photomask for forming gate lines. Referring to FIG. 1A, the conventional photomask 10 for forming the gate lines includes gate line mask patterns 21 and gate tab mask patterns 23 on a substrate 11. An active region 15 is illustrated as an example of where the mask patterns may be situated while forming the gate lines. The gate line mask patterns 21 cross the active region 15, and are parallel to each other. The gate tab mask patterns 23 are located on both sides of the gate line mask patterns 21, and cover the boundary of the active region 15 and an adjacent isolation region. Due to increasing integration of semiconductor devices, active region sizes and channel lengths continue to decrease to a point where hot electron induced punch-through (HEIP) may occur between the active region 15 and the isolation region. Therefore, the gate tab mask patterns 23 are formed to increase the width of the gate lines on the active/isolation region boundary to help prevent HEIP.
Although gate lines 31 are formed using the photomask 21 illustrated in FIG. 1A, the actual pattern formed on a semiconductor device by the technique illustrated above would appear as illustrated in FIG. 1B. Due to optical proximity effects, pattern lengths of gate tabs 33 actually formed on the semiconductor substrate 11 are reduced from the length of the original gate mask patterns 23 and the corners of gate tabs 33 are rounded. As a result, semiconductor device characteristics may suffer from a reduced channel length. Furthermore, and as shown in FIG. 1B, because the gate tabs are in the shape of curve with a peak, the channel length will be further decreased if a misalignment occurs, further deteriorating the semiconductor device characteristics.